Issue link: https://www.e-digitaleditions.com/i/1464345
April/May/June 2022 I 57 Standardization and consensus on thermal measure- ment and testing is critical. Something as simple as the location of the temperature monitor point, where a ther- mocouple is placed, can have a significant impact on the results. For example, if a thermocouple were located at the nose of an active optical transceiver (i.e., the rear end of the transceiver) while the transceiver vendor uses a different location to specify the operational limit, there is a risk of incorrectly predicting the thermal performance, especially when comparing to the actual performance (Figure 4). to significant change from application to application. For this reason, a mandatory prerequisite to any sort of thermal design optimization is to first align and understand the boundary conditions and monitor points of interest. This will help ensure that thermal tests and simulations are completed with a reasonable approach rather than emulating an environment that may be too optimistic or conservative when compared to typical relevant applications. Due to the tight thermal margins available with current designs, it is important to focus on this area. Rack configuration offers another appropriate consideration for data center cooling. As discussed previously, DACs create a larger footprint with wider cables that can block airflow, whereas AECs are thinner and easier to move around in a cabinet. Both are useful for different use cases—shorter lengths versus longer lengths. With traditional fan cooling, the solution cur- rently used in most data center cabinets, changes in cable structure and even where each equipment enclosure sits within the rack can make a huge impact in the overall thermal performance of the data center. FUTURE INNOVATIONS ARE PROVIDING A NEW PATH FORWARD Increasing cooling capability and reducing power consumption are two primary ways to address the chal- lenges of thermal management. While most of this article discussed ways to increase cooling capability through advanced cooling solutions, reducing the power con- sumption is equally beneficial in solving thermal issues. Future technologies provide an encouraging path for- ward regarding the reduction of power consumption. The continued development of silicon can reduce the size and power consumption of a chip, and Moore's law is approaching its end. The continual reduction in transistor size and the ability to pack them in more densely is not a development rule people can rely on anymore. Technologies, such as co-packaged optics (i.e., an innovative option that offers nx100 Gb/s PAM4 optical I/O for Ethernet switch and ML/AI silicon in one assembly), allow for greater signal transfer efficiency between equipment enclosures that also, in theory, reduce the overall power consumption. FIGURE 4: An OCP NIC 3.0 example showing the significant impact of monitor location on the thermal simulation of the QSFP-DD module. This standardization also applies to predictive engi- neering techniques such as computational fluid dynamic (CFD) simulations, where it is imperative to consider and align on the boundary conditions as well as the monitor point. The challenge is that there is no right or wrong for these testing and simulation parameters. They are subject Temperature (°C) Impact of Monitor Point 90 85 80 75 70 65 60 300 Heatsink Base Mean Top Back Shell Module Nose 70°C Criteria 400 500 600 Airflow [LFM] 700 800 900 1000